The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a through via formed therein to penetrate a semiconductor substrate.
In recent years, multi-chip package technology for encapsulating a plurality of semiconductor chips in a single semiconductor package has been developed to reduce a mounting area of a semiconductor device, for example. The encapsulation of a plurality of semiconductor chips in a single semiconductor package enables an increase in the number of lines between chips and an improvement in data transfer rate.
Japanese Unexamined Patent Application Publication No. 2011-145257 discloses an example of a semiconductor device utilizing the multi-chip package technology. In the technique disclosed in Japanese Unexamined Patent Application Publication No. 2011-145257, a semiconductor substrate has a through via (TSV: Through-Silicon Via) formed therein to penetrate the semiconductor substrate. In the semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 2011-145257, a plurality of semiconductor chips is stacked by utilizing the through via. Japanese Unexamined Patent Application Publication No. 2011-145257 discloses a technique for conducting a test to check whether there is a difference in the AC characteristic of the through via by using two semiconductor chips which are stacked vertically.